[Nasm-bugs] [Bug 3392402] New: EVEX relocation offset issue

[no-reply at bugzilla-nasm.gorcunov.org]

https://bugzilla.nasm.us/show_bug.cgi?id=3392402

            Bug ID: 3392402
           Summary: EVEX relocation offset issue
           Product: NASM
           Version: unspecified
          Hardware: All
                OS: All
            Status: OPEN
          Severity: normal
          Priority: Medium
         Component: Assembler
          Assignee: nobody at nasm.us
          Reporter: henrik at gramner.com
                CC: gorcunov at gmail.com, hpa at zytor.com, nasm-bugs at nasm.us

Assembling an EVEX instruction with an address consisting of a base register
plus a relocation offset doesn't seem to work correctly.

Using -f win32 results in "error: COFF format does not support non-32-bit
relocations".

With other output formats it assembles but with an 8-bit offset which is too
small to fit a relocation.

Using identical code except with a VEX-encoded instruction yields the expected
result.

This appears to be related to compressed displacements because adding an offset
which can't be encoded with a compressed displacement seems to work at a quick
glance.

I tried forcing a 32-bit offset by using the dword keyword in the address but
that doesn't seem to affect compressed displacements at all.

Even more weird is that adding a constant offset that's a multiple of the
compressed displacement silently drops the relocation completely.

Test case:

    foo:
    vmovdqa32 zmm0, [eax+foo]       ; error
    vmovdqa32 zmm0, [dword eax+foo] ; (no difference)
    vmovdqa32 zmm0, [eax+foo+1]     ; possibly ok?
    vmovdqa32 zmm0, [eax+foo+64]    ; drops 'foo' completely
    vmovdqa32 zmm0, [eax+64]        ; equal to the above

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