[Nasm-bugs] [Bug 3392703] New: SUBSD/MULSD does not support 64-bit memory operands

[noreply-nasm at dev.nasm.us]

https://bugzilla.nasm.us/show_bug.cgi?id=3392703

            Bug ID: 3392703
           Summary: SUBSD/MULSD does not support 64-bit memory operands
           Product: NASM
           Version: 2.15 (development)
          Hardware: PC
                OS: Linux
            Status: OPEN
          Severity: major
          Priority: Medium
         Component: Assembler
          Assignee: nobody at nasm.us
          Reporter: nemeth.marton at hotmail.com
                CC: chang.seok.bae at intel.com, gorcunov at gmail.com,
                    hpa at zytor.com, nasm-bugs at nasm.us
     Obtained from: From OS distribution

Created attachment 411794
  --> https://bugzilla.nasm.us/attachment.cgi?id=411794&action=edit
Patch file to fix the bug

As you can see in the following example, NASM can assemble ADDSD, but fails to
asseble the SUBSD/MULSD instruction, when using a 64-bit memory reference as
the second operand.

```
sh-5.0$ cat test.S
BITS 64
addsd xmm1, qword[rax]
subsd xmm1, qword[rax]
mulsd xmm1, qword[rax]
sh-5.0$ nasm test.S
test.S:3: error: mismatch in operand sizes
test.S:4: error: mismatch in operand sizes
```

I think I found the root cause in the source code: in `x86/insns.dat`, ADDSD
has the `SQ` flag, while SUBSD and MULSD does not have it. I added the flags,
rebuilt NASM, and now it can assemble all the instructions:

```
sh-5.0$ ~/projects/nasm/nasm test.S
sh-5.0$ r2 -q0 -c 'pd 3' test
            0x00000000      f20f5808       addsd xmm1, qword [rax]
            0x00000004      f20f5c08       subsd xmm1, qword [rax]
            0x00000008      f20f5908       mulsd xmm1, qword [rax]
```

I attached the git patch file which got it working.

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