[nasm:nasm-2.15.xx] x86/insns.dat: add tuple type for the latest AVX512 instructions

nasm-bot for H. Peter Anvin hpa at zytor.com
Fri Jul 17 17:48:05 PDT 2020


Commit-ID:  1d8c09b24e4204767f2d05047e2ac16dcdf46bfb
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=1d8c09b24e4204767f2d05047e2ac16dcdf46bfb
Author:     H. Peter Anvin <hpa at zytor.com>
AuthorDate: Fri, 17 Jul 2020 17:44:27 -0700
Committer:  H. Peter Anvin <hpa at zytor.com>
CommitDate: Fri, 17 Jul 2020 17:44:27 -0700

x86/insns.dat: add tuple type for the latest AVX512 instructions

Add missing tuple type (all are Full - fv:) for the latest AVX512
instructions.

Signed-off-by: H. Peter Anvin (Intel) <hpa at zytor.com>


---
 x86/insns.dat | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/x86/insns.dat b/x86/insns.dat
index 2776cfdf..141d68b3 100644
--- a/x86/insns.dat
+++ b/x86/insns.dat
@@ -6015,20 +6015,20 @@ XRESLDTRK	void				[	f2 0f 01 e9]				TSXLDTRK,FUTURE
 XSUSLDTRK	void				[	f2 0f 01 e8]				TSXLDTRK,FUTURE
 
 ;# AVX512 Bfloat16 instructions
-VCVTNE2PS2BF16	xmmreg|mask|z,xmmreg*,xmmrm128|b32	[rvm:	evex.128.f2.0f38.w0 72 /r]	AVX512BF16,FUTURE
-VCVTNE2PS2BF16	ymmreg|mask|z,ymmreg*,ymmrm256|b32	[rvm:	evex.256.f2.0f38.w0 72 /r]	AVX512BF16,FUTURE
-VCVTNE2PS2BF16	zmmreg|mask|z,zmmreg*,zmmrm512|b32	[rvm:	evex.512.f2.0f38.w0 72 /r]	AVX512BF16,FUTURE
-VCVTNE2PS2BF16	xmmreg|mask|z,xmmreg*,xmmrm128|b32	[rvm:	evex.128.f3.0f38.w0 72 /r]	AVX512BF16,FUTURE
-VCVTNE2PS2BF16	ymmreg|mask|z,ymmreg*,ymmrm256|b32	[rvm:	evex.256.f3.0f38.w0 72 /r]	AVX512BF16,FUTURE
-VCVTNE2PS2BF16	zmmreg|mask|z,zmmreg*,zmmrm512|b32	[rvm:	evex.512.f3.0f38.w0 72 /r]	AVX512BF16,FUTURE
-VDPBF16PS	xmmreg|mask|z,xmmreg*,xmmrm128|b32	[rvm:	evex.128.f3.0f38.w0 52 /r]	AVX512BF16,FUTURE
-VDPBF16PS	ymmreg|mask|z,ymmreg*,ymmrm128|b32	[rvm:	evex.256.f3.0f38.w0 52 /r]	AVX512BF16,FUTURE
-VDPBF16PS	zmmreg|mask|z,zmmreg*,zmmrm128|b32	[rvm:	evex.512.f3.0f38.w0 52 /r]	AVX512BF16,FUTURE
+VCVTNE2PS2BF16	xmmreg|mask|z,xmmreg*,xmmrm128|b32	[rvm:fv:	evex.128.f2.0f38.w0 72 /r]	AVX512BF16,FUTURE
+VCVTNE2PS2BF16	ymmreg|mask|z,ymmreg*,ymmrm256|b32	[rvm:fv:	evex.256.f2.0f38.w0 72 /r]	AVX512BF16,FUTURE
+VCVTNE2PS2BF16	zmmreg|mask|z,zmmreg*,zmmrm512|b32	[rvm:fv:	evex.512.f2.0f38.w0 72 /r]	AVX512BF16,FUTURE
+VCVTNE2PS2BF16	xmmreg|mask|z,xmmreg*,xmmrm128|b32	[rvm:fv:	evex.128.f3.0f38.w0 72 /r]	AVX512BF16,FUTURE
+VCVTNE2PS2BF16	ymmreg|mask|z,ymmreg*,ymmrm256|b32	[rvm:fv:	evex.256.f3.0f38.w0 72 /r]	AVX512BF16,FUTURE
+VCVTNE2PS2BF16	zmmreg|mask|z,zmmreg*,zmmrm512|b32	[rvm:fv:	evex.512.f3.0f38.w0 72 /r]	AVX512BF16,FUTURE
+VDPBF16PS	xmmreg|mask|z,xmmreg*,xmmrm128|b32	[rvm:fv:	evex.128.f3.0f38.w0 52 /r]	AVX512BF16,FUTURE
+VDPBF16PS	ymmreg|mask|z,ymmreg*,ymmrm128|b32	[rvm:fv:	evex.256.f3.0f38.w0 52 /r]	AVX512BF16,FUTURE
+VDPBF16PS	zmmreg|mask|z,zmmreg*,zmmrm128|b32	[rvm:fv:	evex.512.f3.0f38.w0 52 /r]	AVX512BF16,FUTURE
 
 ;# AVX512 mask intersect instructions
-VP2INTERSECTD	kreg|rs2,xmmreg,xmmrm128|b32		[rvm:	evex.nds.128.f2.0f38.w0 68 /r]	AVX512BF16,FUTURE
-VP2INTERSECTD	kreg|rs2,ymmreg,ymmrm128|b32		[rvm:	evex.nds.256.f2.0f38.w0 68 /r]	AVX512BF16,FUTURE
-VP2INTERSECTD	kreg|rs2,zmmreg,zmmrm128|b32		[rvm:	evex.nds.512.f2.0f38.w0 68 /r]	AVX512BF16,FUTURE
+VP2INTERSECTD	kreg|rs2,xmmreg,xmmrm128|b32		[rvm:fv:	evex.nds.128.f2.0f38.w0 68 /r]	AVX512BF16,FUTURE
+VP2INTERSECTD	kreg|rs2,ymmreg,ymmrm128|b32		[rvm:fv:	evex.nds.256.f2.0f38.w0 68 /r]	AVX512BF16,FUTURE
+VP2INTERSECTD	kreg|rs2,zmmreg,zmmrm128|b32		[rvm:fv:	evex.nds.512.f2.0f38.w0 68 /r]	AVX512BF16,FUTURE
 
 ;# Intel Advanced Matrix Extensions (AMX)
 LDTILECFG	mem512				[m:	vex.128.np.0f38.w0 49 /0]		AMXTILE,FUTURE,SZ,X64


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