[nasm:master] insns: handle late-introduced VEX encoded instructions
nasm-bot for H. Peter Anvin
hpa at zytor.com
Tue Dec 6 13:42:07 PST 2022
Commit-ID: 9f31c844053fff01607cdcbe2e4d2963660d3be6
Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=9f31c844053fff01607cdcbe2e4d2963660d3be6
Author: H. Peter Anvin <hpa at zytor.com>
AuthorDate: Tue, 6 Dec 2022 13:38:33 -0800
Committer: H. Peter Anvin <hpa at zytor.com>
CommitDate: Tue, 6 Dec 2022 13:38:33 -0800
insns: handle late-introduced VEX encoded instructions
For VEX instructions created *after* the corresponding EVEX
instructions, we need the user to either explicitly declare them {vex}
or specifying "cpu latevex".
Signed-off-by: H. Peter Anvin <hpa at zytor.com>
---
asm/assemble.c | 4 +++
asm/assemble.h | 4 ++-
asm/directiv.c | 97 +++++++++++++++++++++++++++++++++++++++++++----------
asm/nasm.c | 7 ++--
include/iflag.h | 14 --------
x86/iflags.ph | 6 +++-
x86/insns-iflags.ph | 24 +++++++++----
x86/insns.dat | 75 +++++++++++++++++++++--------------------
8 files changed, 150 insertions(+), 81 deletions(-)
diff --git a/asm/assemble.c b/asm/assemble.c
index 281e02c0..1880a282 100644
--- a/asm/assemble.c
+++ b/asm/assemble.c
@@ -2552,6 +2552,10 @@ static enum match_result matches(const struct itemplate *itemp,
return MERR_ENCMISMATCH;
break;
default:
+ if (itemp_has(itemp, IF_LATEVEX)) {
+ if (!iflag_test(&cpu, IF_LATEVEX))
+ return MERR_ENCMISMATCH;
+ }
break;
}
diff --git a/asm/assemble.h b/asm/assemble.h
index f47ae032..50706626 100644
--- a/asm/assemble.h
+++ b/asm/assemble.h
@@ -41,7 +41,9 @@
#include "nasm.h"
#include "iflag.h"
-extern iflag_t cpu;
+extern iflag_t cpu, cmd_cpu;
+void set_cpu(const char *cpuspec);
+
extern bool in_absolute; /* Are we in an absolute segment? */
extern struct location absolute;
diff --git a/asm/directiv.c b/asm/directiv.c
index 53422098..901d35c1 100644
--- a/asm/directiv.c
+++ b/asm/directiv.c
@@ -1,6 +1,6 @@
/* ----------------------------------------------------------------------- *
*
- * Copyright 1996-2019 The NASM Authors - All Rights Reserved
+ * Copyright 1996-2022 The NASM Authors - All Rights Reserved
* See the file AUTHORS included with the NASM distribution for
* the specific copyright holders.
*
@@ -59,11 +59,25 @@ struct cpunames {
/* Eventually a table of features */
};
-static iflag_t get_cpu(const char *value)
+static void iflag_set_cpu(iflag_t *a, unsigned int lvl)
{
- iflag_t r;
- const struct cpunames *cpu;
+ a->field[0] = 0; /* Not applicable to the CPU type */
+ iflag_set_all_features(a); /* All feature masking bits set for now */
+ if (lvl >= IF_ANY) {
+ /* This is a hack for now */
+ iflag_set(a, IF_LATEVEX);
+ }
+ a->field[IF_CPU_FIELD] &= ~IF_CPU_LEVEL_MASK;
+ iflag_set(a, lvl);
+}
+
+void set_cpu(const char *value)
+{
+ const char *p;
+ char modifier;
+ const struct cpunames *cpuflag;
static const struct cpunames cpunames[] = {
+ { "default", IF_DEFAULT }, /* Must be first */
{ "8086", IF_8086 },
{ "186", IF_186 },
{ "286", IF_286 },
@@ -96,22 +110,69 @@ static iflag_t get_cpu(const char *value)
{ "ivybridge", IF_FUTURE },
{ "any", IF_ANY },
{ "all", IF_ANY },
- { "default", IF_PLEVEL },
- { NULL, IF_PLEVEL } /* Error and final default entry */
+ { "latevex", IF_LATEVEX },
+ { NULL, IF_DEFAULT } /* End of list */
};
- iflag_clear_all(&r);
-
- for (cpu = cpunames; cpu->name; cpu++) {
- if (!nasm_stricmp(value, cpu->name))
- break;
+ if (!value) {
+ iflag_set_cpu(&cpu, cpunames[0].level);
+ return;
}
- if (!cpu->name)
- nasm_nonfatal("unknown 'cpu' type '%s'", value);
+ p = value;
+ modifier = '+';
+ while (*p) {
+ int len = strcspn(p, " ,");
+
+ while (len && (*p == '+' || *p == '-' || *p == '*')) {
+ modifier = *p++;
+ len--;
+ if (!len && modifier == '*')
+ cpu = cmd_cpu;
+ }
+
+ if (len) {
+ bool invert_flag = false;
+
+ if (len >= 3 && !nasm_memicmp(p, "no", 2)) {
+ invert_flag = true;
+ p += 2;
+ len -= 2;
+ }
- iflag_set_cpu(&r, cpu->level);
- return r;
+ for (cpuflag = cpunames; cpuflag->name; cpuflag++)
+ if (!nasm_strnicmp(p, cpuflag->name, len))
+ break;
+
+ if (!cpuflag->name) {
+ nasm_nonfatal("unknown CPU type or flag '%.*s'", len, p);
+ return;
+ }
+
+ if (cpuflag->level >= IF_CPU_FIRST && cpuflag->level <= IF_ANY) {
+ iflag_set_cpu(&cpu, cpuflag->level);
+ } else {
+ switch (modifier) {
+ case '-':
+ invert_flag = !invert_flag;
+ break;
+ case '*':
+ invert_flag ^= iflag_test(&cmd_cpu, cpuflag->level);
+ break;
+ default:
+ break;
+ }
+
+ iflag_set(&cpu, cpuflag->level);
+ if (invert_flag)
+ iflag_clear(&cpu, cpuflag->level);
+ }
+ }
+ p += len;
+ if (!*p)
+ break;
+ p++; /* Skip separator */
+ }
}
static int get_bits(const char *value)
@@ -358,11 +419,11 @@ bool process_directives(char *directive)
if (!declare_label(value, type, special))
break;
-
+
if (type == LBL_COMMON || type == LBL_EXTERN || type == LBL_REQUIRED)
define_label(value, 0, size, false);
- break;
+ break;
}
case D_ABSOLUTE: /* [ABSOLUTE address] */
@@ -440,7 +501,7 @@ bool process_directives(char *directive)
break;
case D_CPU: /* [CPU] */
- cpu = get_cpu(value);
+ set_cpu(value);
break;
case D_LIST: /* [LIST {+|-}] */
diff --git a/asm/nasm.c b/asm/nasm.c
index 90cd999a..76c70f6d 100644
--- a/asm/nasm.c
+++ b/asm/nasm.c
@@ -131,8 +131,7 @@ struct optimization optimizing =
{ MAX_OPTIMIZE, OPTIM_ALL_ENABLED }; /* number of optimization passes to take */
static int cmd_sb = 16; /* by default */
-iflag_t cpu;
-static iflag_t cmd_cpu;
+iflag_t cpu, cmd_cpu;
struct location location;
bool in_absolute; /* Flag we are in ABSOLUTE seg */
@@ -525,8 +524,8 @@ int main(int argc, char **argv)
timestamp();
- iflag_set_default_cpu(&cpu);
- iflag_set_default_cpu(&cmd_cpu);
+ set_cpu(NULL);
+ cmd_cpu = cpu;
set_default_limits();
diff --git a/include/iflag.h b/include/iflag.h
index a268c9bb..31a0a98c 100644
--- a/include/iflag.h
+++ b/include/iflag.h
@@ -85,7 +85,6 @@ IF_GEN_HELPER(xor, ^)
/*
* IF_ANY is the highest CPU level by definition
*/
-#define IF_PLEVEL IF_ANY /* Default CPU level */
#define IF_CPU_LEVEL_MASK ((IFM_ANY << 1) - 1)
static inline int iflag_cmp_cpu(const iflag_t *a, const iflag_t *b)
@@ -116,19 +115,6 @@ static inline void iflag_set_all_features(iflag_t *a)
memset(p, -1, IF_FEATURE_NFIELDS * sizeof(uint32_t));
}
-static inline void iflag_set_cpu(iflag_t *a, unsigned int cpu)
-{
- a->field[0] = 0; /* Not applicable to the CPU type */
- iflag_set_all_features(a); /* All feature masking bits set for now */
- a->field[IF_CPU_FIELD] &= ~IF_CPU_LEVEL_MASK;
- iflag_set(a, cpu);
-}
-
-static inline void iflag_set_default_cpu(iflag_t *a)
-{
- iflag_set_cpu(a, IF_PLEVEL);
-}
-
static inline iflag_t _iflag_pfmask(const iflag_t *a)
{
iflag_t r;
diff --git a/x86/iflags.ph b/x86/iflags.ph
index ff895360..ffeb8e5b 100644
--- a/x86/iflags.ph
+++ b/x86/iflags.ph
@@ -23,6 +23,7 @@ if_("AR2", "SB, SW, SD applies to argument 2");
if_("AR3", "SB, SW, SD applies to argument 3");
if_("AR4", "SB, SW, SD applies to argument 4");
if_("OPT", "Optimizing assembly only");
+if_("LATEVEX", "Only if EVEX instructions are disabled");
#
# dword bound - instruction feature filtering flags
@@ -141,8 +142,11 @@ if_("SANDYBRIDGE", "Sandy Bridge");
if_("FUTURE", "Ivy Bridge or newer");
if_("IA64", "IA64 (in x86 mode)");
+# Default CPU level
+if_("DEFAULT", "Default CPU level");
+
# Must be the last CPU definition
-if_("ANY", "Any x86 CPU");
+if_("ANY", "Allow any known instruction");
# These must come after the CPU definitions proper
if_("CYRIX", "Cyrix-specific");
diff --git a/x86/insns-iflags.ph b/x86/insns-iflags.ph
index 8b4aa2ad..3c73be99 100644
--- a/x86/insns-iflags.ph
+++ b/x86/insns-iflags.ph
@@ -189,22 +189,32 @@ sub write_iflaggen_h() {
}
print N "\n";
- # The names of fields
+ # The names of flag groups
for ($i = 0; $i <= $#flag_fields; $i++) {
- printf N "#define %-19s %3d /* %-64s */\n",
- 'IF_'.$flag_fields[$i]->[0].'_FIELD',
- $flag_fields[$i]->[1] >> 5,
- sprintf("IF_%s (%d) ... IF_%s (%d)",
+ printf N "/* IF_%s (%d) ... IF_%s (%d) */\n",
$flag_bynum[$flag_fields[$i]->[1]]->[1],
$flag_bynum[$flag_fields[$i]->[1]]->[0],
$flag_bynum[$flag_fields[$i]->[2]]->[1],
- $flag_bynum[$flag_fields[$i]->[2]]->[0]);
+ $flag_bynum[$flag_fields[$i]->[2]]->[0];
+
+ # Bit definitions
+ printf N "#define %-19s %3d\n",
+ 'IF_'.$flag_fields[$i]->[0].'_FIRST',
+ $flag_fields[$i]->[1];
+ printf N "#define %-19s %3d\n",
+ 'IF_'.$flag_fields[$i]->[0].'_COUNT',
+ ($flag_fields[$i]->[2] - $flag_fields[$i]->[1] + 1);
+
+ # Field (uint32) definitions
+ printf N "#define %-19s %3d\n",
+ 'IF_'.$flag_fields[$i]->[0].'_FIELD',
+ $flag_fields[$i]->[1] >> 5;
printf N "#define %-19s %3d\n",
'IF_'.$flag_fields[$i]->[0].'_NFIELDS',
($flag_fields[$i]->[2] - $flag_fields[$i]->[1] + 31) >> 5;
+ print N "\n";
}
- print N "\n";
printf N "#define IF_FIELD_COUNT %d\n", $iflag_words;
print N "typedef struct {\n";
diff --git a/x86/insns.dat b/x86/insns.dat
index 39a8dc7f..17a3f107 100644
--- a/x86/insns.dat
+++ b/x86/insns.dat
@@ -3592,6 +3592,45 @@ SHA256MSG2 xmmreg,xmmrm128 [rm: 0f 38 cd /r ] SHA,FUTUR
SHA256RNDS2 xmmreg,xmmrm128,xmm0 [rm-: 0f 38 cb /r ] SHA,FUTURE
SHA256RNDS2 xmmreg,xmmrm128 [rm: 0f 38 cb /r ] SHA,FUTURE
+;# AVX no exception conversions
+; Must precede AVX-512 versions
+VBCSTNEBF16PS xmmreg,mem16 [rm: vex.128.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
+VBCSTNEBF16PS ymmreg,mem16 [rm: vex.256.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
+VBCSTNESH2PS xmmreg,mem16 [rm: vex.128.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
+VBCSTNESH2PS ymmreg,mem16 [rm: vex.256.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
+VCVTNEEBF162PS xmmreg,mem128 [rm: vex.128.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEEBF162PS ymmreg,mem256 [rm: vex.256.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+VCVTNEEPH2PS xmmreg,mem128 [rm: vex.128.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEEPH2PS ymmreg,mem256 [rm: vex.256.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+VCVTNEOBF162PS xmmreg,mem128 [rm: vex.128.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEOBF162PS ymmreg,mem256 [rm: vex.256.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+VCVTNEOPH2PS xmmreg,mem128 [rm: vex.128.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEOPH2PS ymmreg,mem256 [rm: vex.256.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+VCVTNEPS2BF16 xmmreg,xmmrm128 [rm: vex.128.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEPS2BF16 ymmreg,ymmrm256 [rm: vex.256.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+
+;# AVX Vector Neural Network Instructions
+; Must precede AVX-512 versions
+VPDPBSSD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBSSD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBSSDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBSSDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBSUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBSUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBSUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBSUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBUUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBUUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBUUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBUUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+
+;# AVX Integer Fused Multiply-Add
+; Must precede AVX-512 versions
+VPMADD52HUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,LATEVEX,SX
+VPMADD52HUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,LATEVEX,SY
+VPMADD52LUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,LATEVEX,SX
+VPMADD52LUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,LATEVEX,SY
+
;# AVX-512 mask register instructions
KADDB kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 4a /r ] FUTURE
KADDD kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 4a /r ] FUTURE
@@ -6307,42 +6346,6 @@ VSUBPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.np.map5.w0 5
VSUBSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.f3.map5.w0 5c /r] AVX512FP16,FUTURE
VUCOMISH xmmreg,xmmrm16|sae [rm:t1s: evex.lig.np.map5.w0 2e /r] AVX512FP16,FUTURE
-;# AVX no exception conversions
-VBCSTNEBF16PS xmmreg,mem16 [rm: vex.128.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,SW
-VBCSTNEBF16PS ymmreg,mem16 [rm: vex.256.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,SW
-VBCSTNESH2PS xmmreg,mem16 [rm: vex.128.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,SW
-VBCSTNESH2PS ymmreg,mem16 [rm: vex.256.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,SW
-VCVTNEEBF162PS xmmreg,mem128 [rm: vex.128.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SX
-VCVTNEEBF162PS ymmreg,mem256 [rm: vex.256.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SY
-VCVTNEEPH2PS xmmreg,mem128 [rm: vex.128.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SX
-VCVTNEEPH2PS ymmreg,mem256 [rm: vex.256.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SY
-VCVTNEOBF162PS xmmreg,mem128 [rm: vex.128.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SX
-VCVTNEOBF162PS ymmreg,mem256 [rm: vex.256.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SY
-VCVTNEOPH2PS xmmreg,mem128 [rm: vex.128.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SX
-VCVTNEOPH2PS ymmreg,mem256 [rm: vex.256.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SY
-VCVTNEPS2BF16 xmmreg,xmmrm128 [rm: vex.128.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,SX
-VCVTNEPS2BF16 ymmreg,ymmrm256 [rm: vex.256.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,SY
-
-;# AVX Vector Neural Network Instructions
-VPDPBSSD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SX
-VPDPBSSD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SY
-VPDPBSSDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SX
-VPDPBSSDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SY
-VPDPBSUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SX
-VPDPBSUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SY
-VPDPBSUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SX
-VPDPBSUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SY
-VPDPBUUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SX
-VPDPBUUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SY
-VPDPBUUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SX
-VPDPBUUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SY
-
-;# AVX Integer Fused Multiply-Add
-VPMADD52HUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,SX
-VPMADD52HUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,SY
-VPMADD52LUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,SX
-VPMADD52LUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,SY
-
;# RAO-INT weakly ordered atomic operations
AADD mem32,reg32 [mr: norexw np 0f 38 fc /r ] RAOINT,FUTURE,SD
AADD mem64,reg64 [mr: o64 np 0f 38 fc /r ] RAOINT,FUTURE,SQ,LONG
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