[nasm:nasm-2.16.xx] x86/insns.dat: SHA512-NI VEX support
nasm-bot for Tomasz Kantecki
tomasz.kantecki at intel.com
Mon Jan 29 16:27:05 PST 2024
Commit-ID: 5f684412c74484d322b083857aa1b3919c0a9cf0
Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=5f684412c74484d322b083857aa1b3919c0a9cf0
Author: Tomasz Kantecki <tomasz.kantecki at intel.com>
AuthorDate: Fri, 13 Jan 2023 16:05:47 +0000
Committer: H. Peter Anvin <hpa at zytor.com>
CommitDate: Mon, 29 Jan 2024 16:21:21 -0800
x86/insns.dat: SHA512-NI VEX support
Add support for VEX-encoded SHA512-NI instructions.
Signed-off-by: Tomasz Kantecki <tomasz.kantecki at intel.com>
Signed-off-by: H. Peter Anvin <hpa at zytor.com>
---
test/sha-64.asm | 3 +++
test/sha.asm | 3 +++
x86/iflags.ph | 1 +
x86/insns.dat | 3 +++
4 files changed, 10 insertions(+)
diff --git a/test/sha-64.asm b/test/sha-64.asm
index 6cce663e..6546af76 100644
--- a/test/sha-64.asm
+++ b/test/sha-64.asm
@@ -28,3 +28,6 @@ BITS 64
sha256msg2 xmm2, [rax]
sha256msg2 xmm3, [rax+0x12]
sha256msg2 xmm4, [rax+rbx*2]
+ vsha512rnds2 ymm1, ymm2, xmm0
+ vsha512msg1 ymm1, xmm2
+ vsha512msg2 ymm1, ymm2
diff --git a/test/sha.asm b/test/sha.asm
index 684cadd5..9457e413 100644
--- a/test/sha.asm
+++ b/test/sha.asm
@@ -29,3 +29,6 @@ BITS 32
sha256msg2 xmm2, [eax]
sha256msg2 xmm3, [eax+0x12]
sha256msg2 xmm4, [eax+ebx*2]
+ vsha512rnds2 ymm1, ymm2, xmm0
+ vsha512msg1 ymm1, xmm2
+ vsha512msg2 ymm1, ymm2
diff --git a/x86/iflags.ph b/x86/iflags.ph
index ef2b1b4b..6856a4fe 100644
--- a/x86/iflags.ph
+++ b/x86/iflags.ph
@@ -112,6 +112,7 @@ if_("AVXVNNIINT8", "AVX Vector Neural Network 8-bit integer instructions")
if_("AVXIFMA", "AVX integer multiply and add");
if_("HRESET", "History reset");
if_("SMAP", "Supervisor Mode Access Prevention (SMAP)");
+if_("SHA512", "SHA512 instructions");
# Put these last to minimize their relevance
if_("OBSOLETE", "Instruction removed from architecture");
diff --git a/x86/insns.dat b/x86/insns.dat
index 454924d9..6e937992 100644
--- a/x86/insns.dat
+++ b/x86/insns.dat
@@ -3587,6 +3587,9 @@ SHA256MSG1 xmmreg,xmmrm128 [rm: 0f 38 cc /r ] SHA,FUTUR
SHA256MSG2 xmmreg,xmmrm128 [rm: 0f 38 cd /r ] SHA,FUTURE
SHA256RNDS2 xmmreg,xmmrm128,xmm0 [rm-: 0f 38 cb /r ] SHA,FUTURE
SHA256RNDS2 xmmreg,xmmrm128 [rm: 0f 38 cb /r ] SHA,FUTURE
+VSHA512MSG1 ymmreg,xmmreg [rm: vex.256.f2.0f38.w0 cc /r] SHA512,AVX,FUTURE
+VSHA512MSG2 ymmreg,ymmreg [rm: vex.256.f2.0f38.w0 cd /r] SHA512,AVX,FUTURE
+VSHA512RNDS2 ymmreg,ymmreg,xmmreg [rvm: vex.nds.256.f2.0f38.w0 cb /r] SHA512,AVX,FUTURE
;# AVX no exception conversions
; Must precede AVX-512 versions
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